`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:02:52 01/13/2011 
// Design Name: 
// Module Name:    pc 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module programCounter#(parameter WIDTH = 13)(
	 input clk, // clock
    input [1:0] run_stall_reset_sel_in, // control signel
    output [WIDTH - 1:0] pc_out	// program counter output
    );

reg [WIDTH - 1:0] pc = WIDTH'h0000; 

assign pc_out = pc; 

always@(posedge clk)
begin
	case(run_stall_reset_sel):
	0: pc <= pc + WIDTH;
	1: pc <= pc;
	3: pc <= WIDTH'h0000;
end

endmodule
